Too hot to handle?

During the panel entitled, "Keeping Hot Chips Cool: Are IC Thermal Problems Hot Air?," Devadas Varma, founder and chairman of Calypto and panel moderator, highlighted the growing importance of thermal issues. He queried whether the broader design community needs to worry about it at 32nm and beyond or whether it only impacts a small segment of designs.

The thermal problem
Darvin Edwards of Texas Instruments, Inc. admitted that thermal issues are becoming a major design concern. He said high performance microprocessors are pushing the limits of air cooling with growing die sizes, parasitic leakage powers and higher powers in general, although many design, process and software tricks are being used to slow the increasing power dissipation trend.

Edwards called for more thermal engineers to perform better system-level analysis, better thermal modeling tools and a higher level of accuracy in IC package abstraction to guarantee robust thermal design. "An ultimate goal should be to reduce power consumption per function through smart process design, die design and software optimization," he noted.

Simple metric design
According to Paul Franzon, a professor of electrical and computer engineering at North Carolina State University in Raleigh, the niche in which detailed thermal design matters grows with technology scaling. A key decision is ensuring that thermal design is being conducted with sufficient fidelity before a product fails because of a thermally induced failure. One approach is to develop a simple metric that predicts thermal design needs based on simple design and technology parameters.

"The leakage power goes up by 80 percent with every 10°C increase, and it gets worse with scaling," cited Franzon. "The impact of simplified thermal analysis leads to an underprediction of the clock skew. You also underpredict the power consumption because you underpredict the peaks. Thus, you overpredict the delay, and this will lead to unnecessary power increase," he said.

Possible gains
At 32nm, Stephen Kosonocky, fellow, Advanced Micro Devices Inc., said major performance gains will probably be possible by adding cores, threads and special purpose accelerators. He added that improving single thread performance will also "put pressure" on chip designers to push die temperatures even higher.

At present, Kosonocky noted that, "Thermal modeling is mainly used for floorplanning and package/system planning. As die temperatures are pushed higher, reliability and performance modeling may have to account for local thermal conditions."

He said, "IC thermal problems are real, and hotspots are getting hotter. Thermal gradients across the die are getting larger, and reliability can be affected by increasing hotspots. Monitoring systems and thermal budgets will keep this under control."

He stressed that more trade-offs are made during the high-level design phase. "Detailed thermal-aware floorplanning is a must, and thermal-aware modeling is necessary for trade-off analysis," he said.

Limitations of IC chips
Meanwhile, Alain Weger, advisory engineer, the Optical Communications and High Speed Test Department at the IBM Thomas J. Watson Research Center, said silicon chips, in their operating environment, can reside in one or more of three regimes, namely power-limited, temperature-limited and hotspot-limited. He thus called for an understanding of these regimes and their interaction with design, layout and management.

"What happens if the temperature goes too high? Circuit performance degrades, and leakage current can lead to runaway, reliability issues."

He added that, "Chip timing must close depending on the criteria of the design. That means your power efficiency was once subordinated to timing. Power and power density are collective phenomena while timing is mainly a local phenomenon. Can timing and power constraints be reconciled? Those are the main challenges for the EDA industry."

Valuing thermal integrity
Andrew Yang, CEO and chairman, Apache Design Solutions Inc., said thermal integrity has become more critical with the emergence of system-in-package (SIP) designs, especially for stacked-chip with through-silicon via technologies. "Addressing this challenge requires more accurate chip power estimation and distribution with consideration of process-dependent leakage current and activity-based dynamic power," he added.

From an EDA perspective, Yang highlighted that a unified chip and package solution integrated with the system is needed. He noted that, "For SoC designers, if you are working on CPUs, GPUs or MPUs, you will need to consider putting thermal integrity. If working on SIP, thermal integrity is a must-have."

- Anne-Francoise Pele
EE Times Europe